BIST-based Testing and Diagnosis of LUTs in SRAM-based FPGAs

Hadi Jahanirad, Hanieh Karam


FPGA chips have wide applications in nowadays digital systems. Because of fault prone nature of FPGA chips, testing of them is one of the major challenges for designers. Among various test methods, the Built-in Self-Test (BIST) based ones have shown good performance. In this paper, we presented a BIST-based approach to test LUTs as most vulnerable part of FPGA chip. The BIST-based approach is off-line and has been accomplished within two FPGA configurations. Each configurable logic block (CLB) can be tested independently and there is no handshaking among various CLBs' BIST cores. The proposed BIST architecture has been simulated in HSPICE based on 45-nm CMOS technology. Simulation results shown 100% coverage for single stuck at faults along with 19% area overhead due to additional BIST hardware and 25% increase in leakage power.


FPGA; Internal Testing; BIST; Test Pattern Generator; LUT.


Chmelaf, E. "Fpga interconnect delay fault testing." In Test Conference, 2003. Proceedings. ITC 2003. International, vol. 1, pp. 1239-1247. IEEE. doi: 10.1109/test.2003.1271113

Gruwell, Ammon, Peter Zabriskie, and Michael Wirthlin. "High-speed FPGA configuration and testing through JTAG." In IEEE AUTOTESTCON, 2016, pp. 1-8. IEEE, 2016. Doi: 10.1109/AUTEST.2016.7589601

McCluskey, Edward J. "Built-in self-test techniques." IEEE Design & Test of Computers 2, no. 2 (1985): 21-28. doi: 10.1109/MDT.1985.294856

Agrawal, Vishwani D., Charles R. Kime, and Kewal K. Saluja. "A tutorial on built-in self-test. I. Principles." IEEE Design & Test of Computers 10, no. 1 (1993): 73-82. doi: 10.1109/54.199807

Jamal, Kamran. "Built-in self-test for integrated circuits having read/write memory." U.S. Patent 5,568,437, issued October 22, 1996.

Zorian, Yervant. "Built-in self-test." Microelectronic engineering 49, no. 1-2 (1999): 135-138. doi: 10.1016/s0167-9317(99)00434-7.

Stroud, C., K. Leach, and T. Slaughter. "BIST for Xilinx 4000 and Spartan series FPGAs: a case study." In International Test Conference, pp. 1258-1267. 2003.

Liu, Jing, and S. Simmons. "BIST-diagnosis of interconnect fault locations in FPGA's." In Electrical and Computer Engineering, 2003. IEEE CCECE 2003. Canadian Conference on, vol. 1, pp. 207-210. IEEE, 2003. doi: 10.1109/CCECE.2003.1226379.

Girard, Patrick, Olivier Héron, Serge Pravossoudovitch, and Michel Renovell. "An efficient BIST architecture for delay faults in the logic cells of symmetrical SRAM-based FPGAs." Journal of Electronic Testing 22, no. 2 (2006): 161-172. doi: 10.1007/s10836-4631-1.

Bushnell, Michael, and Vishwani Agrawal. Essentials of electronic testing for digital, memory and mixed-signal VLSI circuits. Vol. 17. Springer Science & Business Media, 2004.

Abramovici, Miron, and Charles E. Stroud. "BIST-based test and diagnosis of FPGA logic blocks." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9, no. 1 (2001): 159-172. doi: 10.1109/92.920830

Atoofian, Ehsan, and Zainalabedin Navabi. "A BIST architecture for FPGA look-up table testing reduces reconfigurations." In null, p. 84. IEEE, 2003. doi: 10.1109/ATS.2003.1250788

Girard, Patrick, Olivier Héron, Serge Pravossoudovitch, and Michel Renovell. "BIST of delay faults in the logic architecture of symmetrical FPGAs." In On-Line Testing Symposium, 2004. IOLTS 2004. Proceedings. 10th IEEE International, pp. 187-192. IEEE, 2004. doi: 10.1109/OLT.2004.1319686.

Yarandi, Mahnaz Sadoughi, Armin Alaghi, and Zainalabedin Navabi. "An optimized BIST architecture for FPGA look-up table testing." In Emerging VLSI Technologies and Architectures, 2006. IEEE Computer Society Annual Symposium on, pp. 2-pp. IEEE, 2006. Doi: 10.1109/ISVLSI.2006.24.

Smith, Jack, Tian Xia, and Charles Stroud. "An automated BIST architecture for testing and diagnosing FPGA interconnect faults." Journal of electronic testing 22, no. 3 (2006): 239-253. doi: 10.1007/s10836-006-9319-7.

Dutt, Shantanu, Vinay Verma, and Vishal Suthar. "Built-in-self-test of FPGAs with provable diagnosabilities and high diagnostic coverage with application to online testing." IEEE Transactions on Computer-Aided Design of integrated circuits and systems 27, no. 2 (2008): 309-326. doi: 10.1109/TCAD.2007.906992.

Dutton, Bradley F., and Charles E. Stroud. "Built-in self-test of configurable logic blocks in Virtex-5 FPGAs." In System Theory, 2009. SSST 2009. 41st Southeastern Symposium on, pp. 230-234. IEEE, 2009. doi: 10.1109/SSST.2009.4806778.

Lotfi, Atieh, Parisa Kabiri, and Zainalabedin Navabi. "Configurable architecture for memory BIST." In Design & Test Symposium (EWDTS), 2011 9th East-West, pp. 1-5. IEEE, 2011. Doi: 10.1109/EWDTS.2011.6116571.

Saraswathi, T., K. Ragini, and Ganapathy Reddy Ch. "A review on power optimization of linear feedback shift register (LFSR) for low power built in self-test (BIST)." In Electronics Computer Technology (ICECT), 2011 3rd International Conference on, vol. 6, pp. 172-176. IEEE, 2011. doi: 10.1109/ICECTECH.2011.5942075.

Ruan, Aiwu, Shi Kang, Yu Wang, Xiao Han, Zujian Zhu, Yongbo Liao, and Peng Li. "A Built-In Self-Test (BIST) system with non-intrusive TPG and ORA for FPGA test and diagnosis." Microelectronics Reliability 53, no. 3 (2013): 488-498. doi: 10.1016/j.microrel.2012.09.013.

Mohammadi, Marzieh, Somayeh Sadeghi-Kohan, Nasser Masoumi, and Zainalabedin Navabi. "An off-line MDSI interconnect BIST incorporated in BS 1149.1." In Test Symposium (ETS), 2014 19th IEEE European, pp. 1-2. IEEE, 2014. Doi: 10.1109/ETS.2014.6847847.

Yuvaraja, P., P. Madhavan, and S. Pavithra. "A Review on Concurrent and Non-Concurrent BIST Architecture for Error Detection." Int. J. Novel. Res. Eng & Pharm. Sci 2: 30-33.

Mishra, Bharti, Rita Jain, and Richa Saraswat. "Low power BIST based multiplier design and simulation using FPGA." In Electrical, Electronics and Computer Science (SCEECS), 2016 IEEE Students' Conference on, pp. 1-6. IEEE, 2016. doi: 10.1109/SCEECS.2016.7509284.

Kuon, Ian, Russell Tessier, and Jonathan Rose. "FPGA architecture: Survey and challenges." Foundations and Trends in Electronic Design Automation 2, no. 2 (2008): 135-253. doi: 10.1561/1000000005.

Kaviani, Alireza, and Stephen Brown. "Hybrid FPGA architecture." In Proceedings of the 1996 ACM Fourth International Symposium on Field-Programmable Gate Arrays, pp. 3-9. ACM, 1996. doi: 10.1145/228370.228371.

Mano, M. Morris. Digital design. EBSCO Publishing, Inc., 2002.

Shen, Shu, Riccardo Tinivella, Marco Pirola, Giovanni Ghione, and Vittorio Camarchia. "SPICE library for low-cost RFID applications based on pentacene organic FET." In Wireless Communications Networking and Mobile Computing (WiCOM), 2010 6th International Conference on, pp. 1-4. IEEE, 2010. doi: 10.1109/WICOM.2010.5601134.

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DOI: 10.28991/ijse-01125


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