A Novel Fully Differential Second Generation Current Conveyor and Its Application as a Very High CMRR Instrumentation Amplifier

This paper aims to introduce a novel Fully Differential second generation Current Conveyor (FDCCII) and its application to design a novel Low Power (LP), very high CMRR, and wide bandwidth (BW) Current Mode Instrumentation Amplifier (CMIA). In the proposed application, CMRR, as the most important feature, has been greatly improved by using both common mode feed forward (CMFF) and common mode feedback (CMFB) techniques, which are verified by a perfect circuit analysis. As another unique quality, it neither needs well-matched active blocks nor matched resistors but inherently improves CMRR, BW, and power consumption hence gains an excellent matchless choice for integration. The FDCCII has been designed using 0.18 um TSMC CMOS Technology with ±1.2 V supply voltages. The simulation of the proposed FDCCII and CMIA have been done in HSPICE LEVEL 49. Simulation results for the proposed CMIA are as follow: Voltage CMRR of 216 dB, voltage CMRR BW of 300 Hz. Intrinsic resistance of X-terminals is only 45 Ω and the power dissipation is 383.4 μW. Most favourably, it shows a constant differential voltage gain BW of 18.1 MHz for variable gains (here ranging from 0 dB to 45.7 dB for example) removing the bottleneck of constant gain-BW product of Voltage mode circuits.


2-Proposed FDCCII
Functional block diagram and operational matrix of an ideal FDCCII are shown in Figure 1 and Equation 1, respectively.[ Given Figure 1 and Equation 1, ideal FDCCIIs are current mode building blocks with six terminals that named as Y+, Y-, X+, X-, Z+ and Z-.Ideally the differential voltage of the X-terminals, Vxd, follows the differential voltage of the Y-terminals, Vyd, and the differential current of the Z-terminals, izd, follows the differential current of the X-terminals, ixd.It means that ideal input impedance of Y-terminals, input (output) impedance of X-terminals and output impedance of Z-terminals are infinite, zero, and infinite, respectively.In real conditions, undesirable effects in FDCCII's function results from the non-ideal impedances in these terminals.
The CMOS transistor level realization of the proposed FDCCII is shown in Figure 2. Since this FDCCII has been intended for applications of instrumentation amplifier, thus, the design has been focused to improve its voltage CMRR.Like the most of already reported FDCCIIs, the voltage following operation of this FDCCII depends on the equalizing rate of output currents of two included transconductors.Practically, transistors M1-M2 and M5-M6 as the differential pairs of input stage transconductors must be tightly matched for a unity differential voltage gain from Y to X terminal.This differential pairs share the active loads M25-M26.
The transistors M4, M7 have been employed to fix common mode voltage of nodes B and C by using CMFF technique resulting in voltage CMRR improvement (by the factor of ε4, as is explained in section 3).Actually these pairs, in addition to current mirror M24-M26, generate currents equal to common mode currents of M2 and M5 result in fix common mode voltages of nodes B and C.Moreover, the transistors M3 and M8 have been employed to fix common mode voltages of nodes (X+, X-) and (B, C) by using CMFB technique results in voltage CMRR improvement.Any common mode voltage at X-terminals causes common mode currents in M3 and M8 that along with current mirror M24-M26 generate the same currents in transistors M25-M26 resulting in fixated common mode voltages at nodes (X+, X-) and (B,C) (by the factor of ε4, as is explained in section 3).To prevent the common mode voltage amplifying in drains of M11 (dM11) and M12 (dM12) (by the factor of ε5+ ε6 , as is explained in section 3), a CMFF technique has been employed as the pair of M29-M30 and current mirrors of M11-M13 as follows: The pair of M29-M30 apply a current equal to the common mode current of M27 and M28 to current mirror M11-M13, then there is no common mode current passing through impedances of nodes dM11 and dM12.Transistors M21-M22 that must be matched for symmetry, are the voltage buffer stages.Two identical class-A output stages consisting of M33 and M34 are the current buffer stages.These stages mirror X-terminals differential current to Z-terminals and for a unity differential current gain must be matched with corresponding transistors of the X-terminals branches (M31-M32).In the current following action of the output stages, simple current mirror M18-M20 along with transistors M35-M36 remove common mode currents passing through Z-terminals (by the factor of ε2+ε3-ε1 as is explained in section 3) using the same CMFF technique as the one is already explained.
Driving the mentioned current buffer and voltage buffer blocks (see Figure 2) are determined by vocm which is generated by the CMFB block consisting of current mirror M16-M17 and differential pair of M37-M38 (see Figure 2).Function of the CMFB block is to fix common mode voltage of X-terminals to zero using negative feedback structure.By applying common mode voltage to Y-terminals, the common mode voltage of X-terminals is increased which flows a common mode current in the external resistance of Rx and increasing the common mode voltage in node Vicm.This increased voltage stimulates differential pair of M37-M38 to increase Vocm, resulting in identical common mode currents in M14-M15.Finally, this negative feedback prevents the passing of input common mode current through M21-M22 resulting in great improvement of CMRR.It is worth mentioning that in this work, R ' x is an external resistor placed between X terminals (that is shown as two series resistors of Rx in Figure 2) to form the suitable X inputs and Z outputs currents, thus should sufficiently be larger than internal resistance of X-terminals (rx).

3-Circuit Equations
In this section, a full small signal analysis of the circuit performance is expressed.All transistors of the novel FDCCII are assumed to be operating in saturation region.It should be noticed that transistors M11-M12, M14-M15, M18-M19 and M25-M26 function as constant and variable current sources respectively for differential and common mode inputs.This is because of parallel connected pairs of M3-M4, M7-M8, M29-M30, M35-M36 (which don't respond to differential inputs) and Vicm which is zero for differential inputs.
If differential voltage of Y+ -Y-= Vd (Y+ = -Y-=Vd/2) is applied to Y-terminals, Equations 2 to 4 could be concluded for FDCCII circuit (in this case gm5-8 = gm5 and gm1-4 = gm1 and no ′  between X-terminals are assumed): Using Equations 2 to 4, differential voltage gain from Y-terminals to X-terminals (while there is no external resistor ′  between X-terminals) can be found as Equation 5: Assuming gm1=gm5, results a unity differential voltage gain from Y to X terminals.Using loop gain of differential negative feedback (c.f.denominator of Equation 5) assists to find X-terminals intrinsic floating resistance Because of unity differential current gain of the output stage, the differential voltage gain from Y-terminals to each one of Z-terminals (when there are external resistor of ′  between X-terminals and external grounded loads of Rz at Zterminals) could be expressed as Equation 7: Assuming gm1=gm5 and a constant ′  , the differential voltage gain of   of Equation 7becomes mainly determined by the ratio of RZ ∕/   .Similarly, if common mode voltages of Y+ = Y-= Vcm are applied to the voltage inputs of the FDCCII, the small signal equations for conveying input signals to X-terminals can be expressed as follows (assuming, gm1 = gm5): 1 Now the total common mode voltage gain from Y-terminals to Z-terminals (while there are external resistor of ′  between X-terminals and external grounded loads of Rz at Z-terminals) can be concluded as Equation 11: Loop gain of feedback in the denominator of Equation 11 is very smaller than "one", thus, can be ignored.Finally using Equations 6 and 12 gives voltage CMRR as Equation 13: Transistors dimensions of the proposed FDCCII is shown in Table 1.The dimensions have been optimized for loads of Rz+ = Rz-= RL=1 kΩ.

4-Proposed CMIA and Simulation Results
The novel FDCCII has been improved specifically towards the application of instrumentation amplifier.Thus it can be used alone as an IA when both of its Z-terminals are connected to a grounded load resistor RL.Configurations of the proposed CMIA for voltage input case is shown in Figure 3.The most important specifications of the proposed circuit have been evaluated using HSPICE LEVEL 49 in 0.18 um TSMC CMOS Technology.It should be noticed that ′  = 0.44 kΩ and Vbias = 600 mV (bias voltage connected to gate of M9 in Figure 2) has been used in the simulations.The results of the frequency response simulation at the several gains are shown in Figure 4 for voltage input case.Different gains are obtained (from 0 dB to 45.7 dB) using different values of the load resistors RL (RL =0.44KΩ-150KΩ).It can be seen that the BW is constant as 18.1MHz for different gains (the amount of RL to maintain the same BW for differential voltage gain is limited to 150 KΩ).Favorably, Figure 4 shows that in the designed FDCCII there is no dependency between BW and gain, which exists in Voltage Mode (VM) circuits; the variation in the RL that results in the same variation in the voltage gain has no effect on the BW.The frequency responses of the voltage CMRR is shown in Figure 5.As it can be seen in Figure 5, the proposed CMIA has a CMRR of 216 dB with -3 dB BW of 300 Hz; with RL=1 KΩ, ′  =0.44KΩ.Table 2 summarizes the performance simulation results of the proposed CMIA.Differential voltage gain varies from 0dB (RL=0.44KΩ) to 45.7dB (RL=150KΩ).Power consumption under ±1.2V supply voltage is only 383.4 µW, and Xterminals intrinsic floating resistance (  ) is 45 Ω.The performance comparison between the proposed CMIA and some other artworks is summarized in Table 3.As it can be seen in Table 3, the proposed CMIA exhibits superior performance in terms of CMRR value and differential gain BW for voltage input, very low (  ) and low consumed power.Also, it doesn't need matched blocks.

Table 3 .
Comparison between the proposed CMIA and some other works c for