An Offset-free High linear Low Power High Speed Four-Quadrant MTL Multiplier

In this paper a new CMOS current-mode four-quadrant analog multiplier circuit is proposed. The major advantages of this design are high linearity, high speed and low power consumption. Removing dc offset is the most important improvement in this topology. The circuit is designed with 1.8V supply voltage and is simulated using HSPICE simulator by level 49 parameters in 0.18μm standard CMOS TSMC technology. The aspect ratios of the MOSFETs are optimized using Evolutionary algorithm by MATLAB. The simulation results of this analog multiplier demonstrate a maximum linearity error of 2.6%, a THD of 1.77%, maximum power consumption of 157 μW, -3dB bandwidth of 241MHz and almost free from dc offset.


2-Structure and Theoretical Analysis of the Proposed Multiplier
The proposed multiplier circuit is shown in Figure1.This circuit is driven by a bias part consisting M1 and M2 diode connected MOSFETs that secures VSL as the bias voltage of main part of the circuit.Alternatively, VSL (also VGG) can be provided by VDD through a suitable divided resistor network.Current sources of (x-y) and (x+y) are the input signals of this circuit and IOfo and IOfi are the current sources to cancel the offset errors as will be further discussed later.One of the most important nonidealities of the Mos transistors that mainly causes current errors and nonlinearity in current mirror blocks is channel modulation problem.It is regularly produced by either unequal VDS of basic pair transistors of the current mirror (i.e.M4A-M5A, M4B-M5B and the like here) or/and low output impedance of the current mirror.To guarantee both above-mentioned privileges to sustain, transistors M3A, M6A, M14, M6B ,M3B in bottom half and the likes in top half of the multiplier are inserted.In addition, high swing low voltage cascode current mirrors are used to further increase the dynamic range and reduce the distortion of the proposed circuit.Thus elaborately realizing all above explained plans has greatly secured the less current error and nonlinearity of the proposed multiplier.Now assuming all transistors of this structure are well matched, working in saturation region and have the same trasconductance parameters, then applying MTL translinear principle to both traslinear loops of M1, M2, M3A, M4Aand M1, M2, M3B, M4B in saturation region [5] gives: On the other hand: Then to relate output current to input ones and bias current of I1, Equation 3. is expanded as: Substituting (2-A) in (1-A) and squaring both sides gives:

( )
Then Squaring (5) and simplify the result yields: Similarly I3B can be extracted as: Equation 8. illustrates that the proposed circuit can either be used as a divider by changing (I1) to a variable parameter or as a multiplier otherwise.In Some applications where there is no need for division, the bias circuit can be replaced by dc voltage source VSL .Equation 9. illustrates that changing the voltage of VSL affects the output current slope; so, the slope of the output current would be voltage controlled.However, current controling of the output current can either be achieved by variation of I1 current source.

() 2
The mismatch between NMOS and PMOS transistors and even between the same type of transistors effect of VDS on drain current plus imbalance between pathes fom input to output cause unexpected phenomena such as offset.Offset can change the circuit's output response and is one of the significant source of error in the circuit.As it is shown in Figure .2, the crossing point is not exactly on zero and the more is the deviation of this crossing point from zero the larger would be the offset value.This offset consists of two components.To cancel this unwanted phenomena, two offset currents of IOfi and IOFo are applied to the proposed circuit as is shown Figure 1.These offset currents affect the offset of the circuit by changing the current coming to the input and output nodes.Changing the input node's current by IOfi reduces horizontal offset and change the current in the output by IOFo decreases vertical offset.In practice, these compensating offset values should be applied off chip to the same shown points by proper tunable intermediate current sources.The simpelest tuneable current source which can generate offset currents is shown in Figure 3. in which, by changing POTref as a tunable resistance, the output current can be changed.

3-Simulation Results
To verify the performance of the proposed circuit of Figure1.HSPICE is used to simulate the proposed circuit using level 49 parameters in 0.18  standard CMOS TSMC technology and 1.8V supply voltage.theaspect ratios of MOS transistors are listed in table.1 the values of which are optimized by such evelotionary algorithm as is described in [6].The bias values of the circuit are also given in Table 2.As can be seen in Figure 4, the maximum error is less than 2.5%.

Figure 2 .Figure 3 .
Figure 2. Simulated DC transfer characteristics (Iy is used as sweep parameter)

Figure 4 .
Figure 4. Simulation result of proposed current multiplier circuit and error measurementThe input signals are the sine function with different frequencies of 1 and 10 .As can be seen in Figure4, the maximum error is less than 2.5%.

Figure 5 .
Figure 5. proves that change in VSL causes variation on the output current slope.

Figure 5 .
Figure 5. VSL effect on the output current slopeThe offset canceled DC transfer function which has the most linear response is shown in Figure6.

Figure 6 .
Figure 6.Offset canceled DC transfer characteristicsThe Total Harmonic Distortion (THD) versus input current signal at 1  remains far below 1.7% as is shown in Figure7.